1. Field of the Invention
The present invention relates to a semiconductor device such as a thin film transistor ("TFT"), more particularly, a method of forming a double-layered electrode on a substrate of a semiconductor device.
2. Description of the Related Art
Generally, a semiconductor device such as a liquid crystal display ("LCD") is made through a plurality of process steps. More particularly, in the case of a TFT LCD, such a semiconductor device is made through even more complicated steps. That is, to make a TFT panel, more then six masking processes are required, and more than four masking processes are required for making a color filter. This results in a total of more than 10 masking processes being required for making the TFT LCD.
A method of reducing the number of required masking processes and preventing a short circuit occurring during a photolithography process has been developed. More particularly, a method of reducing the number of masking processes has been developed in forming an electrode layer on a substrate.
FIGS. 1a to 1e illustrate, in cross-section, a portion of a TFT as it undergoes sequential processing steps for forming an electrode layer.
Referring first to FIG. 1a, an aluminum layer 2 for a gate of a TFT element and a photoresist 3 are deposited on a substrate 1 in this order. Next, as shown in FIG. 1b, the photoresist 3 is developed to have a predetermined pattern 3' through a light exposing process, after which the aluminum layer 2 is etched using the photoresist pattern 3' as a mask. After this step, the patterned photoresist layer 3' is removed, thereby obtaining a lower electrode layer 4.
Following the above steps, as shown in FIG. 1c, a molybdenum layer 6 is deposited on the substrate 1 to cover the lower electrode layer 4, after which a photoresist layer 7 is deposited on the molybdenum layer 6.
The photoresist 7 is developed in a predetermined patterned photoresist 7' such that it corresponds to the lower electrode layer 4 but has a width greater than the lower electrode layer 4. After this step, the molybdenum layer 6 is etched using the patterned photoresist layer 7' as a mask such that an upper electrode layer 8 is formed to cover the lower electrode layer 4 (see FIG. 1d). The patterned photoresist layer 7' is then removed, thereby obtaining a double-layered electrode layer 9 as shown in FIG. 1e.
The double-layered electrode layer 9 has the advantages of preventing the breaking of the electrode layer 9 and preventing abnormal growth of an insulating layer to be deposited thereon, thereby preventing the breakdown of the TFT.
However, in the above described electrode forming method, since two masking processes are required, manufacturing productivity is low.
In an effort to solve this problem, a method for simultaneously etching two gate metal layers has been developed.
Describing more in detail with reference to FIGS. 2a to 2c, an aluminum layer 10 and a molybdenum layer 11 are first deposited on a substrate 1 in this order, after which a photoresist 12 is deposited on the molybdenum layer 11 (see FIG. 2a).
Next, the photoresist 12 is developed in a predetermined pattern 13, then the molybdenum layer 11 and the aluminum layer 10 are simultaneously etched by a mixed acid-based etching solution while using the patterned photoresist 13 as a mask, thereby obtaining upper and lower electrode layers 14 and 15 (see FIG. 2b). This method is advantageous in that the number of masking processes is reduced.
However, in this method, since the aluminum layer 10 has a relatively large etch rate, the amount of the side etch of the aluminum layer 10 becomes larger than that of the molybdenum layer 11. Therefore, the upper electrode layer 14 formed of the aluminum layer 10 has a section having a width which is increasingly enlarged in a downward direction, while a width of the upper electrode layer 14 formed of the molybdenum layer 11 becomes larger than that of the lower electrode layer 15, thereby forming an overhang 16. Then the photoresist 13 is removed and an insulating layer is deposited on the upper electrode layer 14.
As shown in FIG. 2c, the overhang 16 causes insufficient covering of the dual-layered electrode 14 and 15 by the insulating layer 17. That is, a void 19 may be formed between the lower electrode layer 15 and the insulating layer 17.
Japanese Laid-Open Patent Publication Nos. S63-077086 and H04-213427 disclose methods for solving the overhang problem. However, these methods also require many etching steps.